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1 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation sp6137h features 3v to 28v step down achieved using dual input on-board 1.5 ? sink (2 ? source) nfet drivers up to 25a ouput capability small 10-pin msop package highly integrated design, minimal components uvlo detects both v cc and v in short circuit protection with auto-restart programmable soft start fast transient response high efficiency: greater than 94% possible a synchronous start-up into a pre-charged output dual supply synchronous buck controller description the sp6137h is a synchronous step-down switching regulator controller optimized for high efficiency. the part is designed to be especially attractive for dual supply, 12v step down with 5v used to power the controller. this lower v cc voltage minimizes power dissipation in the part. the sp6137h is designed to drive a pair of external nfets using a fixed 600khz frequency, pwm voltage mode architecture. protection features include uvlo, thermal shutdown and output short circuit protection. the sp6137h is available in the cost and space saving 10-pin msop . preliminary typical application circuit 8 7 6 5 1 2 3 4 css 47nf cbst 1 f fds6676s 14.5a, 6.0m ? c3 47 f 6.3v r1 68.1k, 1% v out v in 0.8v - 3.3v 0 - 10 a r2 21.5k, 1% c vcc 10 f 6.3v r3 221k, 1% r4 100k, 1% cf1 100pf cz2 820pf cp1 56pf fs=900khz rz2 40.2k, 1% fds6676s 14.5a, 6m ? 8 7 6 5 4 1 2 3 dbst mbr0530 sp6137h 1 2 3 4 5 10 9 8 7 6 vcc gl gnd vfb comp bst gh swn ss uvin uv in v cc gnd 3 rlf 3.0,5% u1 c vcc ceramic 8050 x5r qt ss gnd2 c3, c4 ceramic 1210 x5r c4 47 f 6.3v rz3 4.64k, 1% cz3 220pf c1 22 f 16v c2 22 f 16v gnd v in 3.5v - 28v c1, c2 ceramic 1210 x5r v out =(r1/r2 +1)v fb r5 bead qb = 5v @ 30ma 0.8v v cc gl gnd v fb comp sp6137h 10 pin msop 1 2 3 4 5 10 9 8 7 6 bst gh swn ss uvin now available in lead free packaging applications 12v dpa communications systems graphics cards
2 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation parameter min typ max units ? conditions quiescent current v cc supply current 1.5 3 ma v fb =0.9v (no switching) bst supply current 0.2 0.4 ma ? v fb =0.9v (no switching) protection: uvlo v cc uvlo start threshold 4.00 4.25 4.5 v ? v cc uvlo stop threshold 3.80 4.05 4.4 v ? v cc uvlo hysteresis 200 mv uvin start threshold 2.3 2.5 2.65 v ? uvin stop threshold 2.0 2.2 2.35 v ? uvin hysteresis 300 mv error amplifier reference error amplifier reference 0.792 0.800 0.808 v 2x gain config., measure comp/2 error amplifier reference 0.788 0.800 0.812 v over line and temperature ? error amplifier transconductance 6 ms error amplifier gain 60 db no load comp sink current 150 av fb = 0.9v, comp = 0.9v comp source current 150 av fb = 0.7v, comp = 2.2v v fb input bias current 50 200 na ? v fb = 0.8v internal pole 4 mhz comp clamp 2.5 v v fb =0.7v, t a = 25 c comp clamp temp. coefficient -2 mv/ c control loop: pwm comparator, ramp & loop delay path ramp amplitude 0.92 1.1 1.28 v ? ramp offset 1.1 v t a = 25 c, ramp comp until gh starts switching ramp offset temp. coefficient -2 mv/ c gh minimum pulse width 90 180 ns ? maximum controllable duty ratio 92 97 % ? maximum duty ratio measured just before pulse skipping begins maximum duty ratio 100 % valid for 20 cycles internal oscillator frequency 840 900 960 khz ? electrical specifications unless otherwise specified: 0 c < t amb < 70 c, 4.5v < v cc < 5.5v, bst=v cc ,swn = gnd = 0v, uvin = 3.0v, cv cc = 10 f, c comp = 0.1 f, cgh = cgl = 3.3nf, c ss = 50nf, typical measured at v cc =5v. the ? denotes the specifications which apply over the full operating temperature range, unless otherwise specified. these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc .................................................................................................. 7v bst ............................................................................................... 22v bst-swn ......................................................................... -0.3v to 7v swn ................................................................................... -1v to 15v gh ......................................................................... -0.3v to bst+0.3v gh-swn ......................................................................................... 7v all other pins .......................................................... -0.3v to v cc +0.3v peak output current < 10us gh,gl ............................................................................................. 2a storage temperature .................................................. -65 c to 150 c power dissipation .......................................................................... 1w lead temperature (soldering, 10 sec) ...................................... 300 c esd rating .......................................................................... 2kv hbm thermal resistance ............................................................. 41.9 c/w absolute maximum ratings 810 900 940
3 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation parameter min typ max units ? conditions timers: softstart ss charge current: 10 a ss discharge current: 1 ma ? fault present, ss = 0.2v protection: short circuit & thermal short circuit threshold voltage 0.2 0.25 0.3 v ? measured v ref (0.8v) - v fb hiccup timeout 100 ms v fb = 0v number of allowable clock cycles 20 cycles v fb = 0.7v at 100% duty cycle minimum gl pulse after 20 cycles 0.5 cycles v fb = 0.7v thermal shutdown temperature 145 c thermal recovery temperature 135 c thermal hysteresis 10 c output: nfet gate drivers gh & gl rise times 35 50 ns ? measured 10% to 90% gh & gl fall times 30 40 ns ? measured 90% to 10% gl to gh non overlap time 45 70 ns ? gh & gl measured at 2.0v swn to gl non overlap time 20 30 ns ? measured swn = 100mv to gl = 2.0v gh & gl pull down resistance 50 k ? electrical specifications: continued unless otherwise specified: 0 c < t amb < 70 c, 4.5v < v cc < 5.5v, bst=v cc ,swn = gnd = 0v, uvin = 3.0v, cv cc = 10 f, c comp = 0.1 f, cgh = cgl = 3.3nf, c ss = 50nf, typical measured at v cc =5v. the ? denotes the specifications which apply over the full operating temperature range, unless otherwise specified. pin description pin # pin name description 1v cc bias supply input. connect to external 5v supply. used to power internal circuits and low side gate driver. 2g l high current driver output for the low side nfet switch. it is always low if gh is high or during a fault. resistor pull down ensure low state at low voltage. 3 gnd ground pin. the control circuitry of the ic and lower power driver are referenced to this pin. return separately from other ground traces to the (-) terminal of c out . 4v fb feedback voltage and short circuit detection pin. it is the inverting input of the error amplifier and serves as the output voltage feedback point for the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. whenever v fb drops 0.25v below the positive reference, a short circuit fault is detected and the ic enters hiccup mode. 5 comp output of the error amplifier. it is internally connected to the non-inverting input of the pwm comparator. an optimal filter combination is chosen and connected to this pin and either ground or v fb to stabilize the voltage mode loop. 6 uvin uvlo input for v in voltage. connect a resistor divider between v in and uvin to set minimum operating voltage. 7s s soft start. connect an external capacitor between ss and gnd to set the soft start rate based on the 10 a source current. the ss pin is held low via a 1ma (min) current during all fault conditions. 8 swn lower supply rail for the gh high-side gate driver. connect this pin to the switching node at the junction between the two external power mosfet transistors. 9g h high current driver output for the high side nfet switch. it is always low if gl is high or during a fault. resistor pull down ensure low state at low voltage. 10 bst high side driver supply pin. connect bst to the external boost diode and capacitor as shown in the typical application circuit on page 1. high side driver is connected between bst pin and swn pin.
4 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation general overview the sp6137h is a fixed frequency, voltage mode, synchronous pwm controller optimized for high efficiency. the part has been designed to be especially attractive for split plane applica- tions utilizing 5v to power the controller and 3v to 12v for step down conversion. the heart of the sp6137h is a wide bandwidth transconductance amplifier designed to accom- modate type ii and type iii compensation schemes. a precision 0.8v reference present on the positive terminal of the error amplifier per- mits the programming of the output voltage down to 0.8v via the v fb pin. the output of the error amplifier, comp, compared to a 1.1v peak-to-peak ramp is responsible for trailing edge pwm control. this voltage ramp and pwm control logic are governed by the internal oscil- lator that accurately sets the pwm frequency to 600khz. functional diagram theory of operation the sp6137h contains two unique control fea- tures that are very powerful in distributed appli- cations. first, asynchronous driver control is enabled during start up to prohibit the low side nfet from pulling down the output until the high side nfet has attempted to turn on. sec- ond, a 100% duty cycle timeout ensures that the low side nfet is periodically enhanced during extended periods at 100% duty cycle. this guar- antees the synchronized refreshing of the bst capacitor during very large duty ratios. the sp6137h also contains a number of valu- able protection features. a programmable input (v in ) uvlo allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal v cc uvlo ensures that the controller itself has enough voltage to properly operate. other pro- 1.7 v 1.7 v comparator async. startup 0.4 v f ault clr count 20 clock pulses 900 khz clk clock pulse generator ss gl hold off 100% protection logic q r s reset dominant qpwm clk synchronous driver gnd 3 2 gl pwm loop 5 comp pos ref f ault 1 7 0.8v core reference v cc f ault softstart input ramp = 1.1v vfbint vpos gm gm error amplifier 9 gh 8 swn 10 bst v fb ss 10 a v cc v cc v cc f ault ref ok f ault power fault hiccup fault ref ok vin uvlo vcc uvlo 2.50 von 2.20 v off 6 uvin 4.25 v on 4.05 v off q vcc ref ok 200ms delay counter clr clk r set dominant s + - thermal shutdown 145 ?c on 135 ?c off short circuit detection vfbint + - vpos 0.25 v thermal and short circuit protection uvlo comparators + - + -
5 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation tection features include thermal shutdown and short-circuit detection. in the event that either a thermal, short-circuit, or uvlo fault is de- tected, the sp6137h is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted. under voltage lock out (uvlo) the sp6137h contains two separate uvlo comparators to monitor the bias (v cc ) and con- version (v in ) voltages independently. the v cc uvlo threshold is internally set to 4.25v, whereas the v in uvlo threshold is program- mable through the uvin pin. when the uvin pin is greater than 2.5v, the sp6137h is permit- ted to start up pending the removal of all other faults. both the v cc and v in uvlo compara- tors have been designed with hysteresis to pre- vent noise from resetting a fault. soft start ?oft start?is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source cur- rent. in a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. as a result, excess source current can be defined as the current required to charge the output capacitor. iv in = c out * dv out / dtsoft-start the sp6137h provides the user with the option to program the soft start rate by tying a capacitor from the ss pin to gnd. the selection of this capacitor is based on the 10ua pull up current present at the ss pin and the 0.8v reference voltage. therefore, the excess source can be redefined as: iv in = c out * dv out *10 a / (c ss * 0.8v) hiccup upon the detection of a power, thermal, or short- circuit fault, the sp6137h is forced into an idle state for 100ms (typical). the ss and comp pins are immediately pulled low, and the gate drivers are held off for the duration of the timeout period. power and thermal faults have to be removed before a restart may be attempted, whereas, a short-circuit fault is internally cleared shortly after the fault latch is set. therefore, a restart attempt is guaranteed every 100ms (typi- cal) as long as the short-circuit condition per- sists. thermal and short-circuit protection because the sp6137h is designed to drive large nfets running at high current, there is a chance that either the controller or power converter will become too hot. therefore, an internal thermal shutdown (145 c) has been included to prevent the ic from malfunctioning at extreme tempera- tures. a short-circuit detection comparator has also been included in the sp6137h to protect against the accidental short or sever build up of current at the output of the power converter. this com- parator constantly monitors the positive and negative terminals of the error amplifier, and if the v fb pin ever falls more than 250mv (typi- cal) below the positive reference, a short-circuit fault is set. because the ss pin overrides the internal 0.8v reference during soft start, the sp6137h is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. error amplifier and voltage loop as stated before, the heart of the sp6137h voltage error loop is a high performance, wide bandwidth transconductance amplifier. because of the amplifier? current limited (+/-150 a) transconductance, there are many ways to com- pensate the voltage loop or to control the comp pin externally. if a simple, single pole, single theory of operation: continued
6 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation theory of operation: continued zero response is required, then compensation can be a simple as an rc to ground. if a more complex compensation is required, then the amplifier has enough bandwidth (45 at 4 mhz) and enough gain (60db) to run type iii compen- sation schemes with adequate gain and phase margins at cross over frequencies greater than 50khz. the common mode output of the error amplifier is 0.9v to 2.2v. therefore, the pwm voltage ramp has been set between 1.1v and 2.2v to ensure proper 0% to 100% duty cycle capability. the voltage loop also includes two other very important features. one is an asynchronous start up mode. basically, the gl driver can not turn on unless the gh driver has attempted to turn on or the ss pin has exceeded 1.7v. this feature prevents the controller from ?ragging down the output voltage during startup or in fault modes. the second feature is a 100% duty cycle timeout that ensures synchronized refreshing of the bst capacitor at very high duty ratios. in the event that the gh driver is on for 20 continuous clock cycles, a reset is given to the pwm flip flop half way through the 21st cycle. this forces gl to rise for the remainder of the cycle, in turn refreshing the bst capacitor. gate drivers the sp6137h contains a pair of powerful 2 ? source and 1.5 ? sink drivers. these state of the art drivers are designed to drive external nfets capable of handling up to 30a. rise, fall, and non-overlap times have all been minized to achieve maximum efficiency. all drive pins gh, gl & swn are monitored continuously to ensure that only one external nfet is ever on at any given time. 90% 10% rise time 2v non-overlap f all time 2v 90% 10% gh(gl) gl(gh) gate driver test conditions v(bst) gh v oltage v(vcc) v(swn) gl v oltage v(vin) 0v -0v -v(diode) v v(vin)+v(vcc) bst v oltage v(vcc) time swn v oltage
7 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation applications information inductor selection there are many factors to consider in selecting the inductor including cost, efficiency, size and emi. in a typical sp6137h circuit, the inductor is chosen primarily for value, saturation current and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. the induc- tor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. a good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. the switching frequency and the inductor oper- ating point determine the inductor value as fol- lows: (max) (max) (max) ) ( out r s in out in out i k f v v v v l ? = where: fs = switching frequency kr = ratio of the ac inductor ripple current to the maximum output current the peak to peak inductor ripple current is: l f v v v v i s in out in out pp (max) (max) ) ( ? = once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency require- ments. the core must be large enough not to saturate at the peak inductor current 2 (max) pp out peak i i i + = and provide low core loss at the high switching frequency. low cost powdered iron cores have a gradual saturation characteristic but can intro- duce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the induc- tance dropping sharply when the peak design current is exceeded. nevertheless, they are pre- ferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. in general, ferrite or molypermalloy materials are better choice for all but the most cost sensitive appli- cations. the power dissipated in the inductor is equal to the sum of the core and copper losses. to mini- mize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. core losses have a more significant contribution at low output cur- rent where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. core loss information is usually available from the magnetic vendor. the copper loss in the inductor can be calculated using the following equation: winding rms l cu l r i p 2 ) ( ) ( = where i l(rms) is the rms inductor current that can be calculated as follows: i l(rms) = i out(max) 1 + 1 ( i pp ) 2 3 i out(max)
8 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation output capacitor selection the required esr (equivalent series resis- tance) and capacitance drive the selection of the type and quantity of the output capacitors. the esr must be small enough that both the resis- tive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. during an output load transient, the output capacitor must supply all the addi- tional current demanded by the load until the sp6137cu adjusts the inductor current to the new value. therefore the capacitance must be large enough so that the output voltage is help up while the inductor current ramps up or down to the value corresponding to the new load current. addi- tionally, the esr in the output capacitor causes a step in the output voltage equal to the current. because of the fast transient response and inher- ent 100% and 0% duty cycle capability provided by the sp6137cu when exposed to output load transient, the output capacitor is typically cho- sen for esr, not for capacitance value. the output capacitor? esr, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. the maxi- mum allowable esr required to maintain a specified output voltage ripple can be calculated by: resr ? v out i pk-pk where: ? v out = peak to peak output voltage ripple i pk-pk = peak to peak inductor ripple current the total output ripple is a combination of the esr and the output capacitance value and can be calculated as follows: ? v out = ( i pp (1 ?d) ) 2 + (i pp r esr ) 2 c out f s where: f s = switching frequency d = duty cycle c out = output capacitance value input capacitor selection the input capacitor should be selected for ripple current rating, capacitance and voltage rating. the input capacitor must meet the ripple current requirement imposed by the switching current. in continuous conduction mode, the source cur- rent of the high-side mosfet is approximately a square wave of duty cycle v out /v in . most of this current is supplied by the input bypass capacitors. the rms value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: i cin(rms) = i out(max) d(1 - d) the worse case occurs when the duty cycle d is 50% and gives an rms current value equal to i out /2. select input capacitors with adequate ripple current rating to ensure reliable operation. the power dissipated in the input capacitor is: ) ( 2 ) ( cin esr rms cin cin r i p = this can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. the input voltage ripple primarily depends on the input capacitor esr and capacitance. ignoring the inductor ripple current, the input voltage ripple can be deter- mined by: 2 ) ( ) ( (max) ) ( in in s out in out max out cin esr out in v c f v v v i r i v ? + = ? applications information: continued
9 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation applications information: continued the capacitor type suitable for the output capac- itors can also be used for the input capacitors. however, exercise extra caution when tantalum capacitors are considered. tantalum capacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are con- nected ?ive?to low impedance power sources. mosfet selection the losses associated with mosfets can be divided into conduction and switching losses. conduction losses are related to the on resistance of mosfets, and increase with the load current. switching losses occur on each on/off transition when the mosfets experience both high current and voltage. since the bottom mosfet switches current from/to a paralleled diode (either its own body diode or a schottky diode), the voltage across the mosfet is no more than 1v during switching transition. as a result, its switching losses are negligible. the switching losses are difficult to quantify due to all the variables affecting turn on/ off time. however, the following equation pro- vides an approximation on the switching losses associated with the top mosfet driven by sp6137h. s out in rss sh f i v c p (max) (max) (max) 12 = where c rss = reverse transfer capacitance of the top mosfet switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. the conduc- tion losses associated with top and bottom mosfets are determined by: d i r p out on ds ch 2 (max) ) ( (max) = ) 1 ( 2 (max) ) ( (max) d i r p out on ds cl ? = where p ch(max) = conduction losses of the high side mosfet p cl(max) = conduction losses of the low side mosfet r ds(on) = drain to source on resistance. the total power losses of the top mosfet are the sum of switching and conduction losses. for syn- chronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side mosfets. for input voltages of 3.3v and 5v, conduction losses often dominate switch- ing losses. therefore, lowering the r ds(on) of the mosfets always improves efficiency even though it gives rise to higher switching losses due to increased c rss . top and bottom mosfets experience unequal conduction losses if their on time is unequal. for applications running at large or small duty cycle, it makes sense to use different top and bottom mosfets. alternatively, parallel multiple mosfets to conduct large duty factor. r ds(on) varies greatly with the gate driver voltage. the mosfet vendors often specify r ds(on) on multiple gate to source voltages (v gs ), as well as provide typical curve of r ds(on) versus v gs . for 5v input, use the r ds(on) specified at 4.5v v gs . at the time of this publication, vendors, such as fairchild, siliconix and international rectifier, have started to specify r ds(on) at v gs less than 3v. this has provided necessary data for designs in which these mosfets are driven with 3.3v and made it possible to use sp6137h in 3.3v only applications. thermal calculation must be conducted to ensure the mosfet can handle the maximum load cur- rent. the junction temperature of the mosfet, determined as follows, must stay below the maxi- mum rating. ja mo sfet a j r p t t (max) (max) ( max) + = where t a(max) = maximum ambient temperature p mosfet(max) = maximum power dissipa- tion of the mosfet r ja = junction to ambient thermal resistance. r ja of the device depends greatly on the board
10 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation layout, as well as device package. significant thermal improvement can be achieved in the maxi- mum power dissipation through the proper design of copper mounting pads on the circuit board. for example, in a so-8 package, placing two 0.04 square inches copper pad directly under the pack- age, without occupying additional board space, can increase the maximum power from approxi- mately 1 to 1.2w. for dpak package, enlarging the tap mounting pad to 1 square inches reduces the r ja from 96 c/w to 40 c/w. applications information: continued schottky diode selection when paralleled with the bottom mosfet, an optional schottky diode can improve efficiency and reduce noises. without this schottky diode, the body diode of the bottom mosfet con- ducts the current during the non-overlap time when both mosfets are turned off. unfortu- nately, the body diode has high forward voltage and reverse recovery problem. the reverse re- covery of the body diode causes additional switching noises when the diode turns off. the schottky diode alleviates these noises and addi- tionally improves efficiency thanks to its low forward voltage. the reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. the power dissipation of the schottky diode is determined by p diode = 2v f i out t nol f s where t nol = non-overlap time between gh and gl. v f = forward voltage of the schottky diode. loop compensation design the open loop gain of the whole system can be divided into the gain of the error amplifier, pwm modulator, buck converter output stage, and feedback resistor divider. in order to cross- over at the selected frequency fco, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. (srz2cz2+1)(sr1cz3+1) (sr esr c out + 1) [s^2lc out +s(r esr +r dc ) c out +1] v in sr1cz2(srz3cz3+1)(srz2cp1+1) v ramp_pp v out (volts) + _ v ref (volts) notes: r esr = output capacitor equivalent series resistance. r dc = output inductor dc resistance. v ramp_pp = sp6132 internal ramp amplitude peak to peak voltage. condition: cz2 >> cp1 & r1 >> rz3 output load resistance >> r esr & r dc r 2 v ref (r 1 + r 2 ) or v out v fbk (volts) t ype iii voltage loop compensation g amp (s) gain block pwm stage g pwm gain block output stage g out (s) gain block v oltage feedback g fbk gain block sp6134 voltage mode control loop with loop dynamic
11 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation applications information: continued the goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec. the first step of compensation design is to pick the loop crossover frequency. high crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. crossover fre- quency should be higher than the esr zero but less than 1/5 of the switching frequency. the esr zero is contributed by the esr associated with the output capacitors and can be deter- mined by: ? z(esr) = 1 2 c out r esr the next step is to calculated the complex con- jugate poles contributed by the lc output filter, ? p(lc) = 1 2 l c out frequency (hz) error amplify gain bandwidth product condition: c22 >> cp1, r1 >> rz3 20 log (rz2/r1) gain (db) 1/6.28(r22) (cz2) 1/6.28 (r1) (cz3) 1/6.28 (r1) (cz2) 1/6.28 (rz2) (cp1) 1/6.28 (rz3) (cz3) bode plot of type iii error amplify compensation. when the output capacitors are of a ceramic type, the sp6137cu evaluation board requires a type iii compensation circuit to give a phase boost of 180 in order to counteract the effects of an under damped resonance of the output filter at the double pole frequency. table 1. input and output stage components selection charts. inductors - surface mount inductor specification inductance manufacturer/part no. series r i sat size inductor type manufaturer (uh) m ? (a) lxw(mm) ht.(mm) website 2.7 easy magnet sc5018-2r7m 4.30 12.0 12.6x12.6 4.5 shielded ferrite core inter-technical.com 2.7 tdk rlf 12560t-2r7n110 4.50 12.2 12.5x12.8 6.0 shielded ferrite core tdk.com 3.3 coilcraft do5010p-332hc 8.60 17.0 14.7x15.2 8.0 unshielded ferrite core coilcraft.com 1.2 easy magnet sc5018-1r2m 1.96 20.0 12.6x12.6 4.5 shielded ferrite core inter-technical.com 1.2 inter-technical sc4015-1r2m 4.37 17.0 10.0x10.0 3.8 shielded ferrite core inter-technical.com 1.5 coilcraft do5010p-152hc 4.00 25.0 14.7x15.2 8.0 unshielded ferrite core coilcraft.com 1.9 tdk rlf 12560t-1r9n120 3.60 13.2 12.5x12.8 6.0 shielded ferrite core tdk.com capacitors -surface mount capacitance manufacturer/part no. esr ripple current size voltage capacitor manufaturer (uf) ? (max) (a)@45 c lxw(mm) ht.(mm) (v) type website 22 tdk c3225x5r1c226m 0.002 4.00 3.2x2.5 2.0 16.0 x5r ceramic tdk.com 47 tdk c3225x5roj476m 0.002 4.00 3.2x2.5 2.5 6.3 x5r ceramic tdk.com mosfet - surface mount mosfet manufacturer/part no. rds (on) id current qg qg voltage foot print manufaturer ? (max) (a) nc(typ) nc(max) (v) website n-channel fairchild semi fds6676s 0.006 14.50 43 60.0 30.0 so-8 fairchildsemi.com n-channel fairchild semi fd7088n3 0.005 21.10 37 48.0 30.0 so-8 fairchildsemi.com n-channel vishay si4336dy 0.004 25.0 32 50.0 30.0 so-8 vishay.com note: components highlighted in bold are those used on the sp6134 evaluation board.
12 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation package: 10 pin msop 1 e1 e pin #1 indentifier must be indicated within this shaded area (d/2 * e1/2) l1 l r1 1 r 1 seating plane gauge plane l2 b b symbol min nom max a-- 1.1 a1 0 - 0.15 a2 0.75 0.85 0.95 b 0.17 - 0.27 c 0.08 - 0.23 d e e1 e e1 l 0.4 0.6 0.8 l1 l2 n-10 - r 0.07 - - r1 0.07 - - ?0o-8o ?1 0o - 15o note: dimensions in (mm) 10 pin msop jedec mo-187 (ba) variation 3.00 bsc 4.90 bsc 3.00 bsc 0.50 bsc 2.00 bsc 0.95 ref 0.25 bsc 1 2 e/2 e1 e d c with plating base metal b section b-b a2 a a1 b
13 date: 1/3/05 sp6137h dual supply, synchronous buck controller ?copyright 2005 sipex corporation corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 ordering information part number temperature package sp6137hcu ............................................. 0 c to +70 c .......................................... 10 pin msop sp6137hcu/tr ....................................... 0 c to +70 c .......................................... 10 pin msop sp6137heu ............................................ -40 c to +85 c ........................................ 10 pin msop sp6137heu/tr ...................................... -40 c to +85 c ........................................ 10 pin msop /tr = tape and reel pack quantity is 2500 for msop. available in lead free packaging. to order add "-l" suffix to part number. example: sp6137heu/tr = standard; SP6137HEU-L/tr = lead free click here to order samples

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